PLL for FPGA based Coherent FSK Demodulation

[krishan]

Hello All

I want to implement a Coherent FSK Demodulator in FPGA(Actel).

It has following specifications:

Logic 1 Sub-Carrier Frequency = 5kHz
Logic 0 Sub-Carrier Frequency = 3kHz

Bit Rate = 100 bits per second

I have chosen the sample rate to be 15ksps.

I'll have to use PLL for getting the coherent demodulation in the receiver.

Can anyone guide me with the proper selection of different PLL blocks and their specifications for this application?? It is very urgent

Krishan.