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Post by calabiyau on Jan 12, 2007 6:16:59 GMT -5
Hi all,
First of all, congratulatios for the whole web page. A lot of effort!!
As you will see, we're looking forward to the sync tutorial...
We are designing a 128TCM QAM receiver. Our idea is to take advantadge from the Digital Downconverters (DDC as GC4016 or similar) to convert from HF to baseband directly ,let's say sampling at 1MHz, then DDC (CIC + decimation filters), and then a DSP system at 50KHz sampling time where the complete receiver will be implmented.
The problem we are guessing is about timing recovery. If we recover the timing at baseband (i.e. recover the 50KHz) and multiply it up to the HF sampling frequency to feed the 1MHz A/D, we will substantially increase the loop time due to the DDC path (order of milisecs).
Therefore we suspect (though we donĀ“t know for sure) that the timing recovery will fail to converge or at least will significantly worse this behaviour.
Will be in this way? Do you know about any source/paper talking about the use of DDC in a QAM receiver down to baseband directly? Any other isuue that we should take care of?
Thanks a lot
Alex Moreno
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Post by tmcdavid on Jan 12, 2007 18:17:41 GMT -5
Alex:
Unless you have some timing pilot mixed wth the QAM baseband, I do not see where you have any choice but to recover bit timing from the data stream. If you find some other way, please post the information.
One approach is to compute the vector delta in phase space for each sample of the I and Q values. The vector magnitude will be small while the vector hovers near the constallation point for a given bit. Then the change between vector samples will grow in magnitude as the bit clock advances to the next constellation point. The scollaped picket fence that results can be used to advance or retard your sampling clock until the bit time boundary splits the peaks of the delta-vector magnitude samples.
This is not the only way, but it is an interesting one that gives pretty quick feedback. You can make the feedback factor variable, to quickly get the initial lock, and then reduce it to reduce the clock jitter due to noise on the channel.
Regards, Terry
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