QPSK modulator

[niravjshah]

I have designed digital devices like UART, done verification of ethernet packet related environment.
Now I want to design a QPSK modulator in HDL(i.e. verilog/sv/VHDL).

I am facing two problems:
1)To do QPSK, binary data should be in bipolar(i.e. NRZ-non return to zero). While in HDL we are having unipolar signal. (i.e. 1/0 form NOT 1/-1 form).
So is there any way in HDL by which I can convert unipolar signal to bi-polar? Or it's not required to have data in bi-polar format?

2)QPSK is nothing but two-BPSK and addition of them. It is possible to generate BPSK signals in two channels. But how will I add them in HDL?

=>Please let me know if the question is not clear to you.

[charan langton]

Shift one of the BPSK signals by 90 degrees and then add the two BPSK signals. Thats a QPSK signal.

[niravjshah]

Hi Admin,
Thank you very much for your reply.I agree with your comment. But my questions are....
1)Is it required to have digital data in bi-polar format if I want to do PSK (BPSK or QPSK)?
If yes, then in HDL we can represent signal in uni-polar format only.
2)Till now whatever references I have seen, as a carrier sine/cosine wave is used. While in HDL we are having square wave only.
So how will I do modulation?

Please tell if you have any reference/link wich can solve my questions. (Perticularly how to do modulation through square wave carier)

Thank you very much,
Nirav

[charan langton]

Nirav,

QPSK required a bipolar signal. I am not familiar with HDL, but is there a way in HDL you can shift the unipolar signal by half the amplitude, then the unipolar will become a BPSK signal. From there you can create the QPSK signal by shifting and adding.

QPSK is created at baseband. Carrier can be anything, sine wave or square wave, the only way it matters that you need to recover it with correct timing. BUt if this is a simulation, then you can certainly do it.

Charan Langton

[tmcdavid]

Nirav:
In our FPGA implementation, we have created a symbol shape that is applied to each bit. The symbol table lists the frequency deviation or phase deviation versus time referenced to the center of the bit time. For bit = 1, we add the symbol to the carrier, for bit equal 0, we subtract the deviation from the carrier.
Regards, Terry

PS. You need to tell if you are implementing offset QPSK or non-offset. The non-offset has a symbol rate of half the average bit rate, with two bits forming each symbol. If this is what you intend, then make a truth table for the four possible combinations of two bits and assign phase shift values to each at quadrature separation. One possibility would be +/- pi/4 and +/- 3pi/4. Then as each bit pair is clock in to your modulator, time-shift the carrier by the time associated with the phase shift. There are many ways to implement, but conceptually visualize generating four carriers, all in quadrature. Then select which one of the four to gate to the output from the two-bit code shifting out of the data buffer. Good luck, T.